1. Field of the Invention
The present invention is directed to a method for the production of a vertical MOS transistor.
2. Discussion of the Related Art
With a view to ever-faster components with higher integration density, the structural sizes of integrated circuits are decreasing from generation to generation. This is also true with regard to CMOS technology. It is generally expected (see, for example, Roadmap of Semiconductor Technology, Solid State Technology 3, 1995), that MOS transistors with a gate length of less than 100 nm will be used around the year 2010.
On the one hand, attempts have been made to scale modern CMOS technology in order to produce planar MOS transistors with such gate lengths (see, for example, A. Hori, H. Nakaoka, H. Umimoto, K. Yamashita, M. Takase, N. Shimizu, B. Mizuno, S. Odanaka, A 0.05 .mu.m-CMOS with Ultra Shallow Source/Drain Junctions Fabricated by 5 keV Ion Implantation and Rapid Thermal Annealing, IEDM 1994, 485 and H. Hu, L. T. Su, Y. Yang, D. A. Antoniadis, H I. Smith, Channel and Source/Drain Engineering in High-Performance sub-0.1 .mu.m NMOSFETs using X-ray lithography, Symp. VLSI Technology, 17, 1994). The production of such planar MOS transistors with a channel length of less than 100 nm requires the use of electron beam lithography and has hitherto been possible only on a laboratory scale. The use of the electron beam lithography leads to a superproportional increase in development costs.
In parallel with this, vertical transistors have been investigated with a view to producing shorter channel lengths (see L. Risch, W. H. Krautschneider, F. Hofmann, H. Schafer, Vertical MOS Transistor with 70 nm channel length, ESSDERC 1995, pages 101 to 104). In this case, layer sequences are formed corresponding to the source, channel and drain, and are annularly surrounded by the gate dielectric and gate electrode. In terms of their radio-frequency and logic properties, these vertical MOS transistors have to date been unsatisfactory in comparison with planar MOS transistors.
German patent no. 196 21 244 has proposed a MOS transistor with reduced stray gate capacitances, which is suitable for radio-frequency applications. In order to produce this vertical transistor, a mesa structure comprising a source region, channel region and drain region in vertical succession is formed on a semiconductor substrate. The gate electrode is formed in such a way that it adjoins the mesa structure only at the channel region. Oxide structures, which embed the gate electrode, are formed below and above the gate electrode at the source and drain regions. The gate capacitances are minimized in this way. In order to produce the oxide structures and the gate electrode, corresponding layers are respectively deposited which cover the mesa. Photoresist is applied on top and planarized. The photoresist is subsequently etched back to an extent that leaves free the upper sides of the mesa. This structured photoresist is subsequently used as a mask in order to structure the underlying layer at the mesa. The thickness of the layer is in each case less than the height of the mesa. Since the planarity is limited by the flow of planarized photoresist, the height of the etching erosion in the further structuring of the photoresist layer by etching is difficult to control.